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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct191 presettable synchronous 4-bit binary up/down counter for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 features synchronous reversible counting asynchronous parallel load count enable control for synchronous expansion single up/down control input output capability: standard i cc category: msi general description the 74hc/hct191 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct191 are asynchronously presettable 4-bit binary up/down counters. they contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. asynchronous parallel load capability permits the counter to be preset to any desired number. information present on the parallel data inputs (d 0 to d 3 ) is loaded into the counter and appears on the outputs when the parallel load ( pl) input is low. as indicated in the function table, this operation overrides the counting function. counting is inhibited by a high level on the count enable ( ce) input. when ce is low internal state changes are initiated synchronously by the low-to-high transition of the clock input. the up/down ( u/d) input signal determines the direction of counting as indicated in the function table. the ce input may go low when the clock is in either state, however, the low-to-high ce transition must occur only when the clock is high. also, the u/d input should be changed only when either ce or cp is high. overflow/underflow indications are provided by two types of outputs, the terminal count (tc) and ripple clock ( rc). the tc output is normally low and goes high when a circuit reaches zero in the count-down mode or reaches 15 in the count-up-mode. the tc output will remain high until a state change occurs, either by counting or presetting, or until u/d is changed. do not use the tc output as a clock signal because it is subject to decoding spikes. the tc signal is used internally to enable the rc output. when tc is high and ce is low, the rc output follows the clock pulse (cp). this feature simplifies the design of multistage counters as shown in figs 5 and 6. in fig.5, each rc output is used as the clock input to the next higher stage. it is only necessary to inhibit the first stage to prevent counting in all stages, since a high on ce inhibits the rc output pulse as indicated in the function table. the timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. this can be a disadvantage of this configuration in some applications. fig.6 shows a method of causing state changes to occur simultaneously in all stages. the rc outputs propagate the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. in this configuration the duration of the clock low state must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes high. since the rc output of any package goes high shortly after its cp input goes high there is no such restriction on the high-state duration of the clock. in fig.7, the configuration shown avoids ripple delays and their associated restrictions. combining the tc signals from all the preceding stages forms the ce input for a given stage. an enable must be included in each carry gate in order to inhibit counting. the tc output of a given stage it not affected by its own ce signal therefore the simple inhibit scheme of figs 5 and 6 does not apply.
december 1990 3 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 quick reference data gnd = 0 v; t amb =25 c; t r =t f =6ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay cp to q n c l = 15 pf; v cc = 5 v 22 22 ns f max maximum clock frequency 36 36 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 31 33 pf
december 1990 4 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 pin description pin no. symbol name and function 3, 2, 6, 7 q 0 to q 3 ?ip-?op outputs 4 ce count enable input (active low) 5 u/d up/down input 8 gnd ground (0 v) 11 pl parallel load input (active low) 12 tc terminal count output 13 rc ripple clock output (active low) 14 cp clock input (low-to-high, edge triggered) 15, 1, 10, 9 d 0 to d 3 data inputs 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 5 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 function table tc and rc function table notes 1. h = high voltage level l = low voltage level i = low voltage level one set-up time prior to the low-to-high cp transition x = dont care - = low-to-high cp transition = one low level pulse = tc goes low on a low-to-high cp transition operating mode inputs outputs pl u/d ce cp d n q n parallel load l l x x x x x x l h l h count up h l i - x count up count down h h i - x count down hold (do nothing) hxhxxno change inputs terminal count state outputs u/d ce cp q 0 q 1 q 2 q 3 tc rc h l l l h h h h l h h l x x x x h h h l l l h h h l l l h h h l l l h h h l l l l h l h h h h h fig.4 functional diagram.
december 1990 6 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 fig.5 n-stage ripple counter using ripple clock. fig.6 synchronous n-stage counter using ripple carry/borrow. fig.7 synchronous n-stage counter with parallel gated carry/borrow.
december 1990 7 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 fig.8 typical load, count and inhibit sequence. sequence load (preset) to binary thirteen; count up to fourteen, fifteen, zero, one and two; inhibit; count down to one, zero, fifteen, fourteen and thirteen. fig.9 logic diagram.
december 1990 8 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 72 26 21 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 fig.10 t phl / t plh propagation delay cp to tc 83 30 24 255 51 43 320 64 54 395 77 65 ns 2.0 4.5 6.0 fig.10 t phl / t plh propagation delay cp to rc 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.11 t phl / t plh propagation delay ce to rc 33 12 10 130 26 22 165 33 28 195 39 33 ns 2.0 4.5 6.0 fig.11 t phl / t plh propagation delay d n to q n 61 22 18 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 fig.12 t phl / t plh propagation delay pl to q n 61 22 18 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 fig.13 t phl / t plh propagation delay u/d to tc 44 16 13 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 fig.14 t phl / t plh propagation delay u/d to rc 50 18 14 210 42 36 265 53 45 315 63 54 ns 2.0 4.5 6.0 fig.14 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.15 t w clock pulse width high or low 125 25 21 28 10 8 155 31 26 195 39 33 ns 2.0 4.5 6.0 fig.10 t w parallel load pulse width low 100 20 17 22 8 6 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.15
december 1990 9 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 t rem removal time pl to cp 35 7 6 8 3 2 45 9 8 55 11 9 ns 2.0 4.5 6.0 fig.15 t su set-up time u/d to cp 205 41 35 50 18 14 255 51 43 310 62 53 ns 2.0 4.5 6.0 fig.17 t su set-up time d n to pl 100 20 17 19 7 6 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.16 t su set-up time ce to cp 140 28 24 44 16 13 175 35 30 210 42 36 ns 2.0 4.5 6.0 fig.17 t h hold time u/d to cp 0 0 0 - 39 - 14 - 11 0 0 0 0 0 0 ns 2.0 4.5 6.0 fig.17 t h hold time d n to pl 0 0 0 - 11 - 4 - 3 0 0 0 0 0 0 ns 2.0 4.5 6.0 fig.16 t h hold time ce to cp 0 0 0 - 28 - 10 - 8 0 0 0 0 0 0 ns 2.0 4.5 6.0 fig.17 f max maximum clock pulse frequency 4.0 20 24 11 33 39 3.2 16 19 2.6 13 15 mhz 2.0 4.5 6.0 fig.10 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
december 1990 10 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. input unit load coefficient d n cp u/d ce, pl 0.5 0.65 1.15 1.5
december 1990 11 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 26 48 60 72 ns 4.5 fig.10 t phl / t plh propagation delay cp to tc 32 51 64 77 ns 4.5 fig.10 t phl / t plh propagation delay cp to rc 19 35 44 53 ns 4.5 fig.11 t phl / t plh propagation delay ce to rc 19 33 41 50 ns 4.5 fig.11 t phl / t plh propagation delay d n to q n 22 44 55 66 ns 4.5 fig.12 t phl / t plh propagation delay pl to q n 27 46 58 69 ns 4.5 fig.13 t phl / t plh propagation delay u/d to tc 23 45 56 68 ns 4.5 fig.14 t phl / t plh propagation delay u/d to rc 24 45 56 68 ns 4.5 fig.14 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.15 t w clock pulse width high or low 16 9 20 24 ns 4.5 fig.10 t w parallel load pulse width low 22 11 28 33 ns 4.5 fig.15 t rem removal time pl to cp 7 1 9 11 ns 4.5 fig.15 t su set-up time u/d to cp 41 20 51 62 ns 4.5 fig.17 t su set-up time d n to pl 20 9 25 30 ns 4.5 fig.16 t su set-up time ce to cp 30 18 38 45 ns 4.5 fig.17 t h hold time u/d to cp 0 - 18 0 0 ns 4.5 fig.17 t h hold time d n to pl 0 - 5 0 0 ns 4.5 fig.16 t h hold time ce to cp 0 - 10 0 0 ns 4.5 fig.17 f max maximum clock pulse frequency 20 33 16 13 mhz 4.5 fig.10
december 1990 12 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 ac waveforms fig.10 waveforms showing the clock (cp) to output (q n ) propagation delays, the clock pulse width and the maximum clock pulse frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.11 waveforms showing the clock and count enable inputs (cp, ce) to ripple clock output ( rc) propagation delays. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.12 waveforms showing the input (d n ) to output (q n ) propagation delays. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
december 1990 13 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 fig.13 waveforms showing the input ( pl) to output (q n ) propagation delays. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.14 waveforms showing the up/down count input ( u/d) to terminal count and ripple clock output (tc, rc) propagation delays. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.15 waveforms showing the parallel load input ( pl) pulse width, removal time to clock (cp) and the output (q n ) transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
december 1990 14 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct191 package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.16 waveforms showing the set-up and hold times from the parallel load input ( pl) to the data input (d n ). the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.17 waveforms showing the set-up and hold times from the count enable and up/down inputs ( ce, u/d) to the clock (cp). the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.

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